A low package resistance and good thermal performance is often desirable for semiconductor devices. This is particularly the case for metal oxide semiconductor field effect transistor (MOSFET) devices, especially vertical conduction power MOSFET devices having gate and source electrodes on one surface of a semiconductor chip and a drain electrode on the opposite surface (as opposed to lateral device devices which have all the electrodes on the top surface). It is also generally desirable to have simple, quick and efficient methods of packaging semiconductor devices. Thus, numerous packaging concepts and methods have been developed in the prior art.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old packaging technology continues as the primary packaging means. Epoxy or solder die attachment along with aluminum or gold wire bonding to a lead frame is still the dominant semiconductor packaging methodology. Advances in semiconductor processing technology, however, have made parasitics (e.g., resistances, capacitances and inductances) associated with conventional packaging techniques more of a performance-limiting factor. In addition, there is a constant demand for ever shrinking package sizes. To best utilize space, the total package footprint is desired to be as close to the semiconductor die size as possible. In the case of conventional flip chip technology, among other shortcomings, electrical connection to the back surface of a vertical conduction die is not easily facilitated without taking up a large amount of space, in addition to extra assembly time. These limitations become quite significant in high current applications such as power switching devices.
U.S. Pat. No. 6,271,060 discloses a process of fabricating a package for a semiconductor device including a metal layer which wraps around the edges of the die to form an electrical connection between a location on the front side of the die and the conductive substrate at the back side. The package is essentially the same size as the die. Initially, a conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer; a nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed. A metal layer is sputtered or evaporated on one side of the stack; the stack is turned over and a similar process is performed on the other side of the stack. The resulting metal layers are deposited on front side of the die and extend along the edges of the die to the edges and back side of the substrate. The metal is not deposited on the surfaces of the overcoat. The strips in the stack are then separated, and the saw cuts in the perpendicular direction are broken to separate the individual dice. A thick metal layer is plated on the sputtered or evaporated layers to establish a good electrical connection between the front side and the terminal on the back side of each die. In an alternative embodiment, a nonconductive substrate is used and vias are formed in the substrate and filled with metal to make electrical contact with the terminal on the back side of the die.
U.S. Pat. No. 6,316,287 discloses a method of fabricating a package for a semiconductor device. The method includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board. The cap is then sawed along the scribe line with a saw whose kerf is small enough not to sever the contact between the metal layers. The dice are thereby completely detached from each other, forming individual semiconductor device packages.
U.S. Pat. No. 6,562,647 discloses a semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.
The wafer level chip scale package such as those disclosed in the preceding prior art package designs is popular in small mounting space, for vertical structure power MOSFET, usually extending the Drain to the Source and Gate surface so as to locate all gate and Source as well as Drain electrodes on same surface. However, this structure is has difficulties with board level mounting and inspection due to all the electrodes not being visible from a side view. Also the disclosed prior arts require the use of an additional supporting substrate, or are not truly wafer level processes.
It is within this context that embodiments of the present invention arise.